--- a/devs/eth/arm/gml/npe/v2_01/cdl/gml_npe_eth_driver.cdl 1970-01-01 01:00:00.000000000 +0100 +++ b/devs/eth/arm/gml/npe/v2_01/cdl/gml_npe_eth_driver.cdl 2007-12-18 00:19:32.000000000 +0100 @@ -0,0 +1,82 @@ +# ==================================================================== +# +# Goramo MultiLink Ethernet and NPE support +# +# ==================================================================== +# ==================================================================== + +cdl_package CYGPKG_DEVS_ETH_ARM_GML_NPE { + display "Goramo MultiLink with builtin NPE Ethernet driver" + parent CYGPKG_IO_ETH_DRIVERS + active_if CYGPKG_IO_ETH_DRIVERS + active_if CYGPKG_HAL_ARM_XSCALE_GML + requires CYGPKG_DEVS_ETH_INTEL_NPE + + include_dir cyg/io + + # FIXME: This really belongs in the INTEL_NPE package + cdl_interface CYGINT_DEVS_ETH_INTEL_NPE_REQUIRED { + display "Intel Network Processor Ethernet driver required" + } + + define_proc { + puts $::cdl_system_header "/***** Ethernet driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_DEVS_ETH_INTEL_NPE_INL " + + puts $::cdl_system_header "#define CYGDAT_DEVS_ETH_INTEL_NPE_CFG " + + puts $::cdl_system_header "/***** Ethernet driver proc output end *****/" + } + + + cdl_component CYGPKG_DEVS_ETH_ARM_GML_NPE_ETH0 { + display "Goramo MultiLink Ethernet port driver for NPE B" + flavor bool + default_value 1 + description " + This option includes the GML Ethernet device driver for + builtin NPE B." + + implements CYGHWR_NET_DRIVERS + implements CYGHWR_NET_DRIVER_ETH0 + implements CYGINT_DEVS_ETH_INTEL_NPE_REQUIRED + + cdl_option CYGDAT_DEVS_ETH_ARM_GML_NPE_ETH0_NAME { + display "Device name for the ETH0 Ethernet port driver" + flavor data + default_value {"\"eth0\""} + description " + This option sets the name of the Ethernet device for a + NPEB-based Ethernet port." + } + } + + cdl_component CYGPKG_DEVS_ETH_ARM_GML_NPE_ETH1 { + display "Goramo MultiLink Ethernet port driver for NPE C" + flavor bool + default_value 1 + description " + This option includes the GML Ethernet device driver for + builtin NPE C." + + implements CYGHWR_NET_DRIVERS + implements CYGHWR_NET_DRIVER_ETH1 + implements CYGINT_DEVS_ETH_INTEL_NPE_REQUIRED + + cdl_option CYGDAT_DEVS_ETH_ARM_GML_NPE_ETH1_NAME { + display "Device name for the ETH1 Ethernet port driver" + flavor data + default_value {"\"eth1\""} + description " + This option sets the name of the Ethernet device for a + NPEC-based Ethernet port." + } + } + + cdl_option CYGSEM_DEVS_ETH_INTEL_NPE_PLATFORM_EEPROM { + display "Platform uses EEPROM or FLASH to hold MAC addresses." + flavor bool + default_value 1 + } +} + --- a/devs/eth/arm/gml/npe/v2_01/include/gml_npe.inl 1970-01-01 01:00:00.000000000 +0100 +++ b/devs/eth/arm/gml/npe/v2_01/include/gml_npe.inl 2007-12-18 00:20:36.000000000 +0100 @@ -0,0 +1,40 @@ +//========================================================================== +// +// Goramo MultiLink Ethernet I/O definitions. +// +//========================================================================== +// Copyright (C) 2007 Krzysztof Halasa +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// It is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +//========================================================================== + +#ifdef CYGPKG_DEVS_ETH_ARM_GML_NPE_ETH1 +#define CYGSEM_INTEL_NPE_USE_ETH1 +#define CYGNUM_ETH1_ETH_ID IX_ETH_PORT_2 +#define CYGNUM_ETH1_PHY_NO 1 +#define CYGDAT_NPE_ETH1_NAME CYGDAT_DEVS_ETH_ARM_GML_NPE_ETH1_NAME +#endif + +#ifdef CYGPKG_DEVS_ETH_ARM_GML_NPE_ETH0 +#define CYGSEM_INTEL_NPE_USE_ETH0 +#define CYGNUM_ETH0_ETH_ID IX_ETH_PORT_1 +#define CYGNUM_ETH0_PHY_NO 0 +#define CYGDAT_NPE_ETH0_NAME CYGDAT_DEVS_ETH_ARM_GML_NPE_ETH0_NAME +#endif + +extern int cyghal_get_npe_esa(int, cyg_uint8 *); + +#define CYGHAL_GET_NPE_ESA(_ethid,_addr,_res) \ + (_res) = cyghal_get_npe_esa((_ethid), (_addr)) --- a/devs/eth/intel/npe/ethDB/v2_01/include/IxEthDB_p.h 2007-12-17 20:58:47.000000000 +0100 +++ b/devs/eth/intel/npe/ethDB/v2_01/include/IxEthDB_p.h 2007-12-17 21:00:03.000000000 +0100 @@ -657,7 +657,7 @@ IX_ETH_DB_PUBLIC UINT32 ixEthDBKeyXORHash(void *macAddress); /* Port updates */ -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBNPEUpdateHandler(IxEthDBPortId portID, IxEthDBFeature type); +IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBNPEUpdateHandler(IxEthDBPortId portID, IxEthDBRecordType type); IX_ETH_DB_PUBLIC void ixEthDBUpdatePortLearningTrees(IxEthDBPortMap triggerPorts); IX_ETH_DB_PUBLIC void ixEthDBNPEAccessRequest(IxEthDBPortId portID); IX_ETH_DB_PUBLIC void ixEthDBUpdateLock(void); --- a/devs/eth/intel/npe/featureCtrl/v2_01/src/IxFeatureCtrl.c 2007-12-17 20:58:47.000000000 +0100 +++ b/devs/eth/intel/npe/featureCtrl/v2_01/src/IxFeatureCtrl.c 2007-12-17 21:00:15.000000000 +0100 @@ -336,7 +336,16 @@ #endif #endif - return (pdId); + /* (((pdId & 0xFFFFFFF0) + ((pdId & 0xF) ? 1 : 0))); + CORE_GEN=010 CPU_REV=0 PROD_NUM PROD_REV + 0x69 05 41 F1 - IXP421 266 MHz BB 011111 1 + 0x69 05 41 D1 - IXP425 400 MHz 011101 1 + 0x69 05 41 C1 - IXP425 533 MHz BDT 011100 1 + 0x69 05 40 4x - IXP435 + 0x69 05 42 0x - IXP465 100000 0 + */ + return (((pdId & 0xFFFFFFF0) + + ((pdId & IX_FEATURE_CTRL_SILICON_STEPPING_MASK) ? 1 : 0))); #else /* Return an invalid value for VxWorks simulation */ return 0xffffffff; --- a/devs/flash/arm/gml/current/cdl/flash_gml.cdl 1970-01-01 01:00:00.000000000 +0100 +++ b/devs/flash/arm/gml/current/cdl/flash_gml.cdl 2007-12-18 00:32:24.000000000 +0100 @@ -0,0 +1,49 @@ +# ==================================================================== +# +# FLASH memory - Hardware support on Goramo MultiLink platform +# +# ==================================================================== +## Copyright (C) 2007 Krzysztof Halasa +## +## This program is free software; you can redistribute it and/or modify it +## under the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## It is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with this program; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +# ==================================================================== + +cdl_package CYGPKG_DEVS_FLASH_GML { + display "Goramo MultiLink platform FLASH memory support" + + parent CYGPKG_IO_FLASH + active_if CYGPKG_IO_FLASH + requires CYGPKG_HAL_ARM_XSCALE_GML + requires CYGPKG_DEVS_FLASH_STRATA + + implements CYGHWR_IO_FLASH_BLOCK_LOCKING + + include_dir cyg/io + + # Arguably this should do in the generic package + # but then there is a logic loop so you can never enable it. + cdl_interface CYGINT_DEVS_FLASH_STRATA_REQUIRED { + display "Generic StrataFLASH driver required" + } + + implements CYGINT_DEVS_FLASH_STRATA_REQUIRED + + define_proc { + puts $::cdl_system_header "/***** gml flash driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_DEVS_FLASH_STRATA_INL " + puts $::cdl_system_header "#define CYGDAT_DEVS_FLASH_STRATA_CFG " + puts $::cdl_system_header "/***** gml flash driver proc output end *****/" + } +} --- a/devs/flash/arm/gml/current/include/gml_strataflash.inl 1970-01-01 01:00:00.000000000 +0100 +++ b/devs/flash/arm/gml/current/include/gml_strataflash.inl 2007-12-18 00:08:33.000000000 +0100 @@ -0,0 +1,44 @@ +#ifndef CYGONCE_DEVS_FLASH_GML_STRATAFLASH_INL +#define CYGONCE_DEVS_FLASH_GML_STRATAFLASH_INL +//========================================================================== +// +// Flash programming - device constants, etc. +// +//========================================================================== +// Copyright (C) 2007 Krzysztof Halasa +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// It is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// + +//========================================================================== + +// The GML has one 16-bit device, StrataFlash 28F128. + +#define CYGNUM_FLASH_DEVICES (1) +#define CYGNUM_FLASH_BASE_MASK (0xFF000000u) // 16 MB + +#define CYGNUM_FLASH_BASE (0x50000000u) +#define CYGNUM_FLASH_WIDTH (16) +#define CYGNUM_FLASH_BLANK (1) + +#include // for CYGHWR_HAL_ARM_BIGENDIAN + +// We have to do some address gymnastics in little-endian mode +#ifndef CYGHWR_HAL_ARM_BIGENDIAN +#define __INV(a) ((flash_t *)((unsigned)(a) ^ 0x2)) +#define CYGHWR_FLASH_WRITE_BUF(a,b) (*__INV(a) = *__INV(b)) +#define CYGHWR_FLASH_READ_QUERY(a) (*__INV(a)) +#endif + +#endif // CYGONCE_DEVS_FLASH_GML_STRATAFLASH_INL --- a/ecos.db 2007-12-17 20:58:48.000000000 +0100 +++ b/ecos.db 2007-12-18 00:29:47.000000000 +0100 @@ -574,6 +574,16 @@ on the IXDP425 platform." } +package CYGPKG_DEVS_FLASH_GML { + alias { "FLASH memory support for Goramo MultiLink" flash_gml } + directory devs/flash/arm/gml + script flash_gml.cdl + hardware + description " + This package contains hardware support for FLASH memory + on the Goramo MultiLink platform." +} + package CYGPKG_DEVS_FLASH_XSENGINE { alias { "FLASH memory support for XSEngine" flash_xsengine } directory devs/flash/arm/xsengine @@ -3003,6 +3013,16 @@ eCos on an Intel XScale IXDP425 network processor evaluation board." } +package CYGPKG_HAL_ARM_XSCALE_GML { + alias { "Goramo MultiLink platform" hal_arm_xscale_gml } + directory hal/arm/xscale/gml + script hal_arm_xscale_gml.cdl + hardware + description " + The Goramo MultiLink HAL package provides the support needed to run + eCos on a Goramo MultiLink platform." +} + package CYGPKG_HAL_ARM_XSCALE_GRG { alias { "Intel XScale Generic Residential Gateway" hal_arm_xscale_grg } directory hal/arm/xscale/grg @@ -4779,6 +4799,20 @@ eCos on an Intel network processor evaluation board." } +target gml { + alias { "Goramo MultiLink platform" gml } + packages { CYGPKG_HAL_ARM + CYGPKG_HAL_ARM_XSCALE_CORE + CYGPKG_HAL_ARM_XSCALE_IXP425 + CYGPKG_HAL_ARM_XSCALE_GML + CYGPKG_DEVS_FLASH_STRATA + CYGPKG_DEVS_FLASH_GML + } + description " + The gml target provides the packages needed to run + eCos on a Goramo MultiLink platform." +} + target XSEngine { alias { "Exys XSEngine Board" XSEngine xsengine } packages { CYGPKG_HAL_ARM @@ -6298,6 +6332,15 @@ description "Ethernet driver for IXDP425 with builtin NPE MAC." } +package CYGPKG_DEVS_ETH_ARM_GML_NPE { + alias { "GML / NPE ethernet driver" + devs_eth_arm_gml_npe gml_npe } + hardware + directory devs/eth/arm/gml/npe + script gml_npe_eth_driver.cdl + description "Ethernet driver for Goramo MultiLink with builtin NPE MAC." +} + package CYGPKG_DEVS_ETH_ARM_IXDPG425_NPE { alias { "IXDPG425 / NPE ethernet driver" devs_eth_arm_ixdpg425_npe ixdpg425_npe } @@ -6343,6 +6386,30 @@ eCos on an Intel network processor evaluation board." } +target gml_npe { + alias { "Goramo MultiLink with NPE ethernet" gmlnpe } + packages { CYGPKG_HAL_ARM + CYGPKG_HAL_ARM_XSCALE_CORE + CYGPKG_HAL_ARM_XSCALE_IXP425 + CYGPKG_HAL_ARM_XSCALE_GML + CYGPKG_DEVS_ETH_INTEL_NPE + CYGPKG_DEVS_ETH_INTEL_NPE_ETHACC + CYGPKG_DEVS_ETH_INTEL_NPE_ETHDB + CYGPKG_DEVS_ETH_INTEL_NPE_ETHMII + CYGPKG_DEVS_ETH_INTEL_NPE_NPEDL + CYGPKG_DEVS_ETH_INTEL_NPE_NPEMH + CYGPKG_DEVS_ETH_INTEL_NPE_OSSERVICES + CYGPKG_DEVS_ETH_INTEL_NPE_QMGR + CYGPKG_DEVS_ETH_INTEL_NPE_FEATURECTRL + CYGPKG_DEVS_ETH_ARM_GML_NPE + CYGPKG_DEVS_FLASH_STRATA + CYGPKG_DEVS_FLASH_GML + } + description " + The gml target provides the packages needed to run + eCos on a Goramo MultiLink platform." +} + target grg_npe { alias { "grg with NPE ethernet" grgnpe } packages { CYGPKG_HAL_ARM --- a/hal/arm/xscale/gml/current/cdl/hal_arm_xscale_gml.cdl 1970-01-01 01:00:00.000000000 +0100 +++ b/hal/arm/xscale/gml/current/cdl/hal_arm_xscale_gml.cdl 2007-12-18 00:31:43.000000000 +0100 @@ -0,0 +1,261 @@ +# ==================================================================== +# +# Goramo MultiLink HAL package +# +# ==================================================================== +cdl_package CYGPKG_HAL_ARM_XSCALE_GML { + display "Goramo MultiLink Platform" + parent CYGPKG_HAL_ARM_XSCALE + implements CYGINT_HAL_ARM_BIGENDIAN + hardware + include_dir cyg/hal + define_header hal_arm_xscale_gml.h + description " + This HAL platform package provides support for + the Goramo MultiLink platform." + + compile gml.c + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H " + puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H " + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H " + puts $::cdl_header "#define CYGBLD_HAL_PLF_INTS_H " + puts $::cdl_header "#define HAL_PLATFORM_CPU \"XScale\"" + puts $::cdl_header "#define HAL_PLATFORM_BOARD \"MultiLink\"" + puts $::cdl_header "#ifdef CYGHWR_HAL_ARM_BIGENDIAN" + puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"BE\"" + puts $::cdl_header "#else" + puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"LE (unsupported)\"" + puts $::cdl_header "#endif" + puts $::cdl_header "#define HAL_PLATFORM_MACHINE_TYPE 1292" + } + + cdl_component CYG_HAL_STARTUP { + display "Startup type" + flavor data + default_value {"RAM"} + legal_values {"RAM" "ROM" } + no_define + define -file system.h CYG_HAL_STARTUP + description " + When targeting the GML platform it is possible to build + the system for either RAM bootstrap or ROM bootstrap(s). Select + 'ram' when building programs to load into RAM using onboard + debug software such as RedBoot or eCos GDB stubs." + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + no_define + description " + Global build options including control over + compiler flags, linker flags and choice of toolchain." + + parent CYGPKG_NONE + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "arm-elf" } + description " + This option specifies the command prefix used when + invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { CYGHWR_HAL_ARM_BIGENDIAN ? "-mbig-endian -mcpu=xscale -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -mapcs-frame" : + "-mcpu=xscale -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -mapcs-frame" } + description " + This option controls the global compiler flags which are used to + compile all packages by default. Individual packages may define + options which override these global flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { CYGHWR_HAL_ARM_BIGENDIAN ? "-mbig-endian -mcpu=xscale -Wl,--gc-sections -Wl,-static -g -O2 -nostdlib" : + "-mcpu=xscale -Wl,--gc-sections -Wl,-static -g -O2 -nostdlib " } + description " + This option controls the global linker flags. Individual + packages may define options which override these global flags." + } + + cdl_option CYGBLD_BUILD_GDB_STUBS { + display "Build GDB stub ROM image" + default_value 0 + requires { CYG_HAL_STARTUP == "ROM" } + requires CYGSEM_HAL_ROM_MONITOR + requires CYGBLD_BUILD_COMMON_GDB_STUBS + requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT + requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT + requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT + requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM + no_define + description " + This option enables the building of the GDB stubs for the + platform. The common HAL controls takes care of most of the + build process, but the final conversion from ELF image to + binary data is handled by the platform CDL, allowing + relocation of the data if necessary." + + make -priority 320 { + /bin/gdb_module.bin : /bin/gdb_module.img + $(OBJCOPY) --remove-section=.fixed_vectors -O binary $< $@ + } + } + } + + cdl_component CYGPKG_HAL_ARM_XSCALE_GML_OPTIONS { + display "Goramo MultiLink build options" + flavor none + no_define + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + cdl_option CYGPKG_HAL_ARM_XSCALE_GML_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building the Goramo MultiLink HAL. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_HAL_ARM_XSCALE_GML_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building the Goramo MultiLink HAL. These flags are removed from + the set of global flags if present." + } + + cdl_option CYGNUM_HAL_BREAKPOINT_LIST_SIZE { + display "Number of breakpoints supported by the HAL." + flavor data + default_value 32 + description " + This option determines the number of breakpoints supported by the HAL." + } + } + + cdl_option CYGSEM_HAL_IXP425_PLF_USES_UART1 { + display "GML uses IXP425 high-speed UART" + flavor bool + default_value 1 + description " + Enable this option if the IXP425 high-speed UART is used + as a virtual vector communications channel." + } + + cdl_option CYGSEM_HAL_IXP425_PLF_USES_UART2 { + display "GML uses IXP425 console UART" + flavor bool + default_value 1 + description " + Enable this option if the IXP425 console UART is to be used + as a virtual vector communications channel." + } + + cdl_component CYGHWR_MEMORY_LAYOUT { + display "Memory layout" + flavor data + no_define + calculated { CYG_HAL_STARTUP == "RAM" ? "arm_xscale_gml_ram" : "arm_xscale_gml_rom" } + + cdl_option CYGHWR_MEMORY_LAYOUT_LDI { + display "Memory layout linker script fragment" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_LDI + calculated { CYG_HAL_STARTUP == "RAM" ? "" : \ + "" } + } + + cdl_option CYGHWR_MEMORY_LAYOUT_H { + display "Memory layout header file" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_H + calculated { CYG_HAL_STARTUP == "RAM" ? "" : \ + "" } + } + } + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + flavor bool + default_value 0 + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "ROM" } + description " + Enable this option if this program is to be used as a ROM monitor, + i.e. applications will be loaded into RAM, and this ROM monitor + may process exceptions or interrupts generated from the + application. This enables features such as utilizing a separate + interrupt stack when exceptions are generated." + } + + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Work with a ROM monitor" + flavor booldata + legal_values { "Generic" "GDB_stubs" } + default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 } + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "RAM" } + description " + Support can be enabled for different varieties of ROM monitor. + This support changes various eCos semantics such as the encoding + of diagnostic output, or the overriding of hardware interrupt + vectors. + Firstly there is \"Generic\" support which prevents the HAL + from overriding the hardware vectors that it does not use, to + instead allow an installed ROM monitor to handle them. This is + the most basic support which is likely to be common to most + implementations of ROM monitor. + \"GDB_stubs\" provides support when GDB stubs are included in + the ROM monitor or boot ROM." + } + + cdl_component CYGPKG_REDBOOT_HAL_OPTIONS { + display "Redboot HAL options" + flavor none + no_define + parent CYGPKG_REDBOOT + active_if CYGPKG_REDBOOT + description " + This option lists the target's requirements for a valid Redboot + configuration." + + cdl_option CYGBLD_BUILD_REDBOOT_BIN { + display "Build Redboot ROM binary image" + active_if CYGBLD_BUILD_REDBOOT + default_value 1 + no_define + description "This option enables the conversion of the Redboot ELF + image to a binary image suitable for ROM programming." + + make -priority 325 { + /bin/redboot.bin : /bin/redboot.elf + $(OBJCOPY) --strip-debug $< $(@:.bin=.img) + $(OBJCOPY) -O srec $< $(@:.bin=.srec) + $(OBJCOPY) -O binary $< $@ + } + } + } +} --- a/hal/arm/xscale/gml/current/include/gml.h 1970-01-01 01:00:00.000000000 +0100 +++ b/hal/arm/xscale/gml/current/include/gml.h 2007-12-17 23:19:35.000000000 +0100 @@ -0,0 +1,95 @@ +#ifndef CYGONCE_HAL_ARM_XSCALE_GML_GML_H +#define CYGONCE_HAL_ARM_XSCALE_GML_GML_H + +/*============================================================================= +// +// Goramo MultiLink platform specific support (register layout, etc) +// +//============================================================================= +// Copyright (C) 2007 Krzysztof Halasa +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// It is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +//===========================================================================*/ + +#include +#include CYGHWR_MEMORY_LAYOUT_H +#include +#include + +// These must match setup in the page table in hal_platform_extras.h +#define SDRAM_PHYS_BASE 0x00000000 +#define SDRAM_BASE 0x00000000 +#define SDRAM_ALIAS_BASE 0x10000000 +#define SDRAM_UNCACHED_BASE 0x20000000 +#define SDRAM_DC_BASE 0x30000000 +#define SDRAM_MAX_SIZE 0x10000000 // 256 MB + +#define FLASH_BASE 0x50000000 +#define FLASH_SIZE 0x01000000 +#define FLASH_DC_BASE 0xA0000000 + +// CS0 (flash timings FIXME */ +#define IXP425_EXP_CS0_INIT \ + (EXP_ADDR_T(3) | EXP_SETUP_T(3) | EXP_STROBE_T(15) | EXP_HOLD_T(3) | \ + EXP_RECOVERY_T(15) | EXP_SZ_16M | EXP_WR_EN | EXP_BYTE_RD16 | EXP_CS_EN) + +// GPIO lines MultiLink Micro router +#define GPIO_SCL 0 +#define GPIO_SDA 1 +#define GPIO_STR 2 +#define GPIO_INPUT1 3 // USB IRQ AUTO +#define GPIO_INPUT2 4 // MDINT0 +#define GPIO_INPUT3 5 // MDINT1 HD/FD +#define GPIO_INPUT4 6 // HSS0_DCD +#define GPIO_INPUT5 7 // HSS1_DCD +#define GPIO_INPUT6 8 // UART0_DCD INT_uP +#define GPIO_INPUT7 9 // UART1_DCD 10/100 +#define GPIO_INPUT8 10 // HSS0_CTS +#define GPIO_INPUT9 11 // HSS1_CTS +#define GPIO_INPUT10 12 // miniPCI IRQ Bridge/Router +#define GPIO_HSS1_RTS_N 13 +#define GPIO_HSS0_RTS_N 14 + +// Control outputs from 74HC4094 +#define CONTROL_HSS0_CLK_INT 0 +#define CONTROL_HSS1_CLK_INT 1 +#define CONTROL_HSS0_DTR_N 2 +#define CONTROL_HSS1_DTR_N 3 // unused on Micro router +#define CONTROL_EXT 4 // unused on Micro router +#define CONTROL_AUTO_RESET 5 // OUT on Micro router +#define CONTROL_PCI_RESET_N 6 // unused on Micro router +#define CONTROL_EEPROM_WC_N 7 + +// offsets from start of flash ROM = 0x50000000 +#define CONFIG_ETH0_ADDRESS 0x40 // 6 bytes +#define CONFIG_ETH1_ADDRESS 0x46 // 6 bytes +#define CONFIG_REV 0x4C // u32 +#define CONFIG_SDRAM_SIZE 0x50 // u32 +#define CONFIG_SDRAM_CONF 0x54 // u32 +#define CONFIG_SDRAM_MODE 0x58 // u32 +#define CONFIG_SDRAM_REFRESH 0x5C // u32 + +#define CONFIG_HW_BITS 0x60 // u32 +#define CONFIG_HW_USB_PORTS 0x00000007 // 0 = no NEC chip, 1-5 = ports# +#define CONFIG_HW_HAS_PCI_SLOT 0x00000008 +#define CONFIG_HW_HAS_ETH0 0x00000010 +#define CONFIG_HW_HAS_ETH1 0x00000020 +#define CONFIG_HW_HAS_HSS0 0x00000040 +#define CONFIG_HW_HAS_HSS1 0x00000080 +#define CONFIG_HW_HAS_UART0 0x00000100 +#define CONFIG_HW_HAS_UART1 0x00000200 +#define CONFIG_HW_HAS_EEPROM 0x00000400 + +#endif // CYGONCE_HAL_ARM_XSCALE_GML_GML_H --- a/hal/arm/xscale/gml/current/include/hal_platform_setup.h 1970-01-01 01:00:00.000000000 +0100 +++ b/hal/arm/xscale/gml/current/include/hal_platform_setup.h 2007-12-17 23:27:06.000000000 +0100 @@ -0,0 +1,277 @@ +#ifndef CYGONCE_HAL_PLATFORM_SETUP_H +#define CYGONCE_HAL_PLATFORM_SETUP_H + +/*============================================================================= +// +// Goramo MultiLink platform specific support for HAL (assembly code) +// +//============================================================================= +// Copyright (C) 2007 Krzysztof Halasa +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// It is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +//===========================================================================*/ + +#include // System-wide configuration info +#include CYGBLD_HAL_VARIANT_H // Variant specific configuration +#include CYGBLD_HAL_PLATFORM_H // Platform specific configuration +#include // Variant specific hardware definitions +#include // MMU definitions +#include // more MMU definitions +#include // Platform specific hardware definitions + +// ------------------------------------------------------------------------ +// Convenience macros for setting up page table +// +.macro IXP_MAP_SDRAM va, c, b, x, p + XSCALE_MMU_SECTION SDRAM_PHYS_BASE>>20, \va>>20, SDRAM_MAX_SIZE>>20, \c, \b, 3, \x, \p +.endm + +.macro IXP_MAP_EXP_V n, va, sz, c, b, x, p + XSCALE_MMU_SECTION (0x500 + ((IXP425_EXP_CS_SIZE * \n) >> 20)), \va>>20, \sz>>20, \c, \b, 3, \x, \p +.endm + +.macro IXP_MAP_EXP n, sz, c, b, x, p + IXP_MAP_EXP_V \n, (0x50000000 + (IXP425_EXP_CS_SIZE * \n)), \sz, \c, \b, \x, \p +.endm + +.macro IXP_MAP_IO addr, sz + XSCALE_MMU_SECTION \addr>>20, \addr>>20, \sz>>20, 0, 0, 3, 0, 0 +.endm + + +#ifdef CYG_HAL_STARTUP_ROM +#define PLATFORM_SETUP1 _platform_setup1 +#define CYGHWR_HAL_ARM_HAS_MMU + +// Delay a bit +.macro DELAY cycles, reg0 + ldr \reg0, =\cycles + subs \reg0, \reg0, #1 + subne pc, pc, #0xc +.endm + +// ------------------------------------------------------------------------ +// This macro represents the initial ROM startup code + .macro _platform_setup1 + +#ifdef CYGHWR_HAL_ARM_BIGENDIAN + // set big-endian + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #0x80 + mcr p15, 0, r0, c1, c0, 0 + CPWAIT r0 +#endif + + ldr r0,=(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE) + msr cpsr, r0 + + // invalidate I & D caches & BTB + mcr p15, 0, r0, c7, c7, 0 + CPWAIT r0 + + // invalidate I & Data TLB + mcr p15, 0, r0, c8, c7, 0 + CPWAIT r0 + + // drain write and fill buffers + mcr p15, 0, r0, c7, c10, 4 + CPWAIT r0 + + // disable write buffer coalescing + mrc p15, 0, r0, c1, c0, 1 + orr r0, r0, #1 + mcr p15, 0, r0, c1, c0, 1 + CPWAIT r0 + + // Setup chip selects + ldr r1, =IXP425_EXP_CFG_BASE + ldr r0, =IXP425_EXP_CS0_INIT + str r0, [r1, #IXP425_EXP_CS0] + + // Enable the Icache + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #MMU_Control_I + mcr p15, 0, r0, c1, c0, 0 + CPWAIT r0 + + // Setup SDRAM controller + + ldr r0, =IXP425_SDRAM_CFG_BASE + ldr r8, =FLASH_BASE + + ldr r1, [r8, #CONFIG_SDRAM_CONF] + str r1, [r0, #IXP425_SDRAM_CONFIG] + + // disable refresh cycles + mov r1, #0 + str r1, [r0, #IXP425_SDRAM_REFRESH] + + // send nop command + mov r1, #SDRAM_IR_NOP + str r1, [r0, #IXP425_SDRAM_IR] + DELAY 0x10000, r1 + + // set SDRAM internal refresh val + ldr r1, [r8, #CONFIG_SDRAM_REFRESH] + str r1, [r0, #IXP425_SDRAM_REFRESH] + DELAY 0x10000, r1 + + // send precharge-all command to close all open banks + mov r1, #SDRAM_IR_PRECHARGE + str r1, [r0, #IXP425_SDRAM_IR] + DELAY 0x10000, r1 + + // provide 8 auto-refresh cycles + mov r1, #SDRAM_IR_AUTO_REFRESH + mov r2, #8 +1: + str r1, [r0, #IXP425_SDRAM_IR] + DELAY 0x800, r3 + subs r2, r2, #1 + bne 1b + + // set mode register in sdram + ldr r1, [r8, #CONFIG_SDRAM_MODE] + str r1, [r0, #IXP425_SDRAM_IR] + DELAY 0x10000, r1 + + // start normal operation + mov r1, #SDRAM_IR_NORMAL + str r1, [r0, #IXP425_SDRAM_IR] + DELAY 0x10000, r1 + + // enable byte swapping control via page table P bit. + ldr r2, =IXP425_EXP_CFG_BASE + ldr r1, [r2, #IXP425_EXP_CNFG1] + orr r1, r1, #EXP_CNFG1_BYTE_SWAP_EN + str r1, [r2, #IXP425_EXP_CNFG1] + + // value to load into pc to jump to real runtime address + ldr r0, =1f + + // setup EXP_CNFG0 value to switch EXP bus out of low memory + ldr r2, =IXP425_EXP_CFG_BASE + ldr r1, [r2, #IXP425_EXP_CNFG0] + bic r1, r1, #EXP_CNFG0_MEM_MAP + + + b icache_boundary + .p2align 5 +icache_boundary: + // Here is where we switch from boot address (0x000000000) to the + // actual flash runtime address. We align to cache boundary so we + // execute from cache during the switchover. Cachelines are 8 words. + str r1, [r2, #IXP425_EXP_CNFG0] // make the EXP bus switch + nop + nop + nop + nop + mov pc, r0 + // We should never reach this point. If we do, + // loop forever. +0: b 0b +1: + // Build mmu tables into RAM so page table walks by the cpu + // don't interfere with FLASH programming. + mov r1, #SDRAM_PHYS_BASE + orr r1, r1, #0x4000 // RAM tables + add r2, r1, #0x4000 // End of tables + + // First clear table + mov r0, #0 +1: + str r0, [r1], #4 + cmp r1, r2 + bne 1b + + // Build section mappings + IXP_MAP_SDRAM SDRAM_BASE, 1, 0, 0, 0 // Cached RAM + IXP_MAP_SDRAM SDRAM_ALIAS_BASE, 1, 0, 0, 0 // Cached RAM alias + IXP_MAP_SDRAM SDRAM_UNCACHED_BASE, 0, 0, 0, 0 // Uncached RAM + IXP_MAP_SDRAM SDRAM_DC_BASE, 1, 0, 0, 1 // Cached data coherent RAM + + IXP_MAP_EXP 0, FLASH_SIZE, 1, 0, 0, 0 // Flash + IXP_MAP_EXP 4, (1 << 20), 0, 0, 0, 0 // NPE use + IXP_MAP_EXP 5, (1 << 20), 0, 0, 0, 0 // NPE use + + IXP_MAP_EXP_V 0, FLASH_DC_BASE, FLASH_SIZE, 1, 0, 0, 1 // data coherent flash + + IXP_MAP_IO IXP425_PCI_WINDOW_BASE, IXP425_PCI_WINDOW_SIZE + IXP_MAP_IO IXP425_QMGR_BASE, IXP425_QMGR_SIZE + IXP_MAP_IO IXP425_PCI_CFG_BASE, IXP425_PCI_CFG_SIZE + IXP_MAP_IO IXP425_EXP_CFG_BASE, IXP425_EXP_CFG_SIZE + IXP_MAP_IO IXP425_MISC_CFG_BASE, IXP425_MISC_CFG_SIZE + IXP_MAP_IO IXP425_SDRAM_CFG_BASE, IXP425_SDRAM_CFG_SIZE + + mcr p15, 0, r0, c7, c10, 4 // drain the write & fill buffers + CPWAIT r0 + + // Set the TTB register to DRAM mmu_table + ldr r0, =(SDRAM_PHYS_BASE | 0x4000) // RAM tables + mcr p15, 0, r0, c2, c0, 0 // load page table pointer + CPWAIT r0 + + // enable permission checks in all domains + ldr r0, =0x55555555 + mcr p15, 0, r0, c3, c0, 0 + CPWAIT r0 + + // enable mmu + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #MMU_Control_M + orr r0, r0, #MMU_Control_R + mcr p15, 0, r0, c1, c0, 0 + CPWAIT r0 + + // enable D cache + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #MMU_Control_C + mcr p15, 0, r0, c1, c0, 0 + CPWAIT r0 + + // Enable branch target buffer + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #MMU_Control_BTB + mcr p15, 0, r0, c1, c0, 0 + CPWAIT r0 + + mcr p15, 0, r0, c7, c10, 4 // drain the write & fill buffers + CPWAIT r0 + + mcr p15, 0, r0, c7, c7, 0 // flush Icache, Dcache and BTB + CPWAIT r0 + + mcr p15, 0, r0, c8, c7, 0 // flush instuction and data TLBs + CPWAIT r0 + + mcr p15, 0, r0, c7, c10, 4 // drain the write & fill buffers + CPWAIT r0 + + // save SDRAM size + ldr r1, =hal_dram_size // [see hal_intr.h] + ldr r8, [r8, #CONFIG_SDRAM_SIZE] + str r8, [r1] + + .endm // _platform_setup1 + +#else // defined(CYG_HAL_STARTUP_ROM) +#define PLATFORM_SETUP1 +#endif + +#define PLATFORM_VECTORS _platform_vectors + .macro _platform_vectors + .endm + +#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */ --- a/hal/arm/xscale/gml/current/include/hal_plf_ints.h 1970-01-01 01:00:00.000000000 +0100 +++ b/hal/arm/xscale/gml/current/include/hal_plf_ints.h 2007-12-17 23:04:57.000000000 +0100 @@ -0,0 +1,30 @@ +#ifndef CYGONCE_HAL_PLF_INTS_H +#define CYGONCE_HAL_PLF_INTS_H +//========================================================================== +// +// Goramo MultiLink HAL platform interrupt support +// +//========================================================================== +// Copyright (C) 2007 Krzysztof Halasa +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// It is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +//========================================================================== + +// start with variant ints +#include CYGBLD_HAL_VAR_INTS_H + +#define HAL_PLATFORM_RESET() CYG_EMPTY_STATEMENT + +#endif // CYGONCE_HAL_PLF_INTS_H --- a/hal/arm/xscale/gml/current/include/pkgconf/mlt_arm_xscale_gml_ram.h 1970-01-01 01:00:00.000000000 +0100 +++ b/hal/arm/xscale/gml/current/include/pkgconf/mlt_arm_xscale_gml_ram.h 2007-12-17 21:00:03.000000000 +0100 @@ -0,0 +1,16 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include +#include + +#endif +#define CYGMEM_REGION_ram (0) +#define CYGMEM_REGION_ram_SIZE (0x02000000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x02000000 - (size_t) CYG_LABEL_NAME (__heap1)) + --- a/hal/arm/xscale/gml/current/include/pkgconf/mlt_arm_xscale_gml_ram.ldi 1970-01-01 01:00:00.000000000 +0100 +++ b/hal/arm/xscale/gml/current/include/pkgconf/mlt_arm_xscale_gml_ram.ldi 2007-12-17 21:00:03.000000000 +0100 @@ -0,0 +1,25 @@ +// eCos memory layout + +#include + +MEMORY +{ + ram : ORIGIN = 0, LENGTH = 0x02000000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA) + SECTION_rom_vectors (ram, 0x80000, LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} --- a/hal/arm/xscale/gml/current/include/pkgconf/mlt_arm_xscale_gml_rom.h 1970-01-01 01:00:00.000000000 +0100 +++ b/hal/arm/xscale/gml/current/include/pkgconf/mlt_arm_xscale_gml_rom.h 2007-12-17 21:00:03.000000000 +0100 @@ -0,0 +1,18 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include +#include + +#endif +#define CYGMEM_REGION_ram (0) +#define CYGMEM_REGION_ram_SIZE (*(unsigned int *)0x50000050) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_rom (0x50000000) +#define CYGMEM_REGION_rom_SIZE (0x60000) +#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x02000000 - (size_t) CYG_LABEL_NAME (__heap1)) --- a/hal/arm/xscale/gml/current/include/pkgconf/mlt_arm_xscale_gml_rom.ldi 1970-01-01 01:00:00.000000000 +0100 +++ b/hal/arm/xscale/gml/current/include/pkgconf/mlt_arm_xscale_gml_rom.ldi 2007-12-17 21:00:03.000000000 +0100 @@ -0,0 +1,28 @@ +// eCos memory layout + +#include + +MEMORY +{ + ram : ORIGIN = 0, LENGTH = 0x02000000 + rom : ORIGIN = 0x50000000, LENGTH = 0x60000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (rom, 0x50000000, LMA_EQ_VMA) /* 0x40 bytes */ + /* 0x40 bytes for configuration information */ + SECTION_text (rom, 0x50000080, LMA_EQ_VMA) + SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_mmu_tables (rom, ALIGN (0x4000), LMA_EQ_VMA) + SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA) + SECTION_data (ram, 0x8000, FOLLOWING (.mmu_tables)) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} --- a/hal/arm/xscale/gml/current/include/plf_io.h 1970-01-01 01:00:00.000000000 +0100 +++ b/hal/arm/xscale/gml/current/include/plf_io.h 2007-12-17 23:27:29.000000000 +0100 @@ -0,0 +1,33 @@ +#ifndef CYGONCE_PLF_IO_H +#define CYGONCE_PLF_IO_H + +//============================================================================= +// +// Goramo MultiLink platform specific IO support +// +//============================================================================= +// Copyright (C) 2007 Krzysztof Halasa +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// It is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +//============================================================================= + +#include +#include // IO macros +#include +#include CYGBLD_HAL_PLF_INTS_H + +//----------------------------------------------------------------------------- +// end of plf_io.h +#endif // CYGONCE_PLF_IO_H --- a/hal/arm/xscale/gml/current/misc/redboot_RAM.ecm 1970-01-01 01:00:00.000000000 +0100 +++ b/hal/arm/xscale/gml/current/misc/redboot_RAM.ecm 2007-12-18 00:21:18.000000000 +0100 @@ -0,0 +1,127 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware gml ; + template redboot ; + package -hardware CYGPKG_HAL_ARM current ; + package -hardware CYGPKG_HAL_ARM_XSCALE_CORE current ; + package -hardware CYGPKG_HAL_ARM_XSCALE_IXP425 current ; + package -hardware CYGPKG_HAL_ARM_XSCALE_GML current ; + package -hardware CYGPKG_DEVS_FLASH_STRATA current ; + package -hardware CYGPKG_DEVS_FLASH_GML current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; + package -template CYGPKG_ISOINFRA current ; + package -template CYGPKG_LIBC_STRING current ; + package -template CYGPKG_CRC current ; + package CYGPKG_IO_FLASH current ; + package CYGPKG_IO_ETH_DRIVERS current ; + package CYGPKG_MEMALLOC current ; + package CYGPKG_COMPRESS_ZLIB current ; +}; + +cdl_component CYG_HAL_STARTUP { + user_value RAM +}; + +cdl_option CYGBLD_BUILD_GDB_STUBS { + user_value 0 +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT { + inferred_value 0 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE { + inferred_value 0x80000 +}; + +cdl_component CYGSEM_REDBOOT_FLASH_CONFIG { + user_value 1 +}; + +cdl_component CYGSEM_REDBOOT_BSP_SYSCALLS { + inferred_value 1 +}; + +cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT { + inferred_value 0x8000 +}; + +cdl_option CYGHWR_HAL_IXP425_PCI_NP_WORKAROUND { + inferred_value 0 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 +}; + +cdl_option CYGPKG_HAL_GDB_FILEIO { + user_value 1 +}; + +cdl_option CYGHWR_REDBOOT_LINUX_EXEC_X_SWITCH { + user_value 1 +} + +cdl_option CYGSEM_REDBOOT_NETWORK_INIT_ONE_DEVICE { + user_value 1 +}; + +cdl_option CYGHWR_HAL_ARM_BIGENDIAN { + user_value 1 +}; + --- a/hal/arm/xscale/gml/current/misc/redboot_ROM.ecm 1970-01-01 01:00:00.000000000 +0100 +++ b/hal/arm/xscale/gml/current/misc/redboot_ROM.ecm 2007-12-18 00:21:25.000000000 +0100 @@ -0,0 +1,136 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware gml ; + template redboot ; + package -hardware CYGPKG_HAL_ARM current ; + package -hardware CYGPKG_HAL_ARM_XSCALE_CORE current ; + package -hardware CYGPKG_HAL_ARM_XSCALE_IXP425 current ; + package -hardware CYGPKG_HAL_ARM_XSCALE_GML current ; + package -hardware CYGPKG_DEVS_FLASH_STRATA current ; + package -hardware CYGPKG_DEVS_FLASH_GML current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; + package -template CYGPKG_ISOINFRA current ; + package -template CYGPKG_LIBC_STRING current ; + package -template CYGPKG_CRC current ; + package CYGPKG_IO_FLASH current ; + package CYGPKG_IO_ETH_DRIVERS current ; + package CYGPKG_MEMALLOC current ; + package CYGPKG_COMPRESS_ZLIB current ; +}; + +cdl_component CYG_HAL_STARTUP { + user_value ROM +}; + +cdl_option CYGBLD_BUILD_GDB_STUBS { + user_value 0 +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT { + inferred_value 0 +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + user_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE { + inferred_value 0x60000 +}; + +cdl_component CYGSEM_REDBOOT_FLASH_CONFIG { + user_value 1 +}; + +cdl_component CYGSEM_REDBOOT_BSP_SYSCALLS { + inferred_value 1 +}; + +cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT { + inferred_value 0x8000 +}; + +cdl_option CYGHWR_HAL_IXP425_PCI_NP_WORKAROUND { + inferred_value 0 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_DNS_HEADER { + inferred_value 1 +}; + +cdl_option CYGPKG_HAL_GDB_FILEIO { + user_value 1 +}; + +cdl_option CYGHWR_REDBOOT_LINUX_EXEC_X_SWITCH { + user_value 1 +} + +cdl_option CYGSEM_REDBOOT_NETWORK_INIT_ONE_DEVICE { + user_value 1 +}; + +cdl_option CYGHWR_HAL_ARM_BIGENDIAN { + user_value 1 +}; + + --- a/hal/arm/xscale/gml/current/src/gml.c 1970-01-01 01:00:00.000000000 +0100 +++ b/hal/arm/xscale/gml/current/src/gml.c 2007-12-17 23:37:35.000000000 +0100 @@ -0,0 +1,159 @@ +//========================================================================== +// +// Goramo MultiLink HAL platform support code +// +//========================================================================== +// Copyright (C) 2007 Krzysztof Halasa +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// It is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +//========================================================================*/ + +#include +#include +#include +#include CYGBLD_HAL_PLATFORM_H + +#include // base types +#include // tracing macros +#include // assertion macros + +#include // IO macros +#include // Register state info +#include +#include // Interrupt names +#include +#include // Hardware definitions +#include // Platform specifics + +#include // diag_printf + +#define CLK_LO() HAL_GPIO_OUTPUT_CLEAR(GPIO_SCL) +#define CLK_HI() HAL_GPIO_OUTPUT_SET(GPIO_SCL) + +#define DATA_LO() HAL_GPIO_OUTPUT_CLEAR(GPIO_SDA) +#define DATA_HI() HAL_GPIO_OUTPUT_SET(GPIO_SDA) + +#define STR_LO() HAL_GPIO_OUTPUT_CLEAR(GPIO_STR) +#define STR_HI() HAL_GPIO_OUTPUT_SET(GPIO_STR) + +static cyg_uint8 control_value = 0; +static inline void set_control(int line, int value) +{ + if (value) + control_value |= (1 << line); + else + control_value &= ~(1 << line); +} + +static void output_control(void) +{ + int i; + + // assume CLK is high + for (i = 0; i < 8; i++) { + CLK_LO(); hal_delay_us(5); + if (control_value & (0x80 >> i)) // MSB first + DATA_HI(); + else + DATA_LO(); + hal_delay_us(5); + CLK_HI(); hal_delay_us(5); // active edge + } + + STR_HI(); hal_delay_us(5); + STR_LO(); hal_delay_us(5); + + CLK_LO(); hal_delay_us(5); + DATA_HI(); hal_delay_us(5); // Be ready for START + CLK_HI(); hal_delay_us(5); +} + +void plf_hardware_init(void) +{ + HAL_GPIO_OUTPUT_ENABLE(15); + + STR_LO(); + HAL_GPIO_OUTPUT_ENABLE(GPIO_STR); + + DATA_LO(); + HAL_GPIO_OUTPUT_ENABLE(GPIO_SDA); + + CLK_HI(); + HAL_GPIO_OUTPUT_ENABLE(GPIO_SCL); + hal_delay_us(5); + + DATA_HI(); + hal_delay_us(5); + + // HSS RTS lines + HAL_GPIO_OUTPUT_SET(GPIO_HSS0_RTS_N); + HAL_GPIO_OUTPUT_ENABLE(GPIO_HSS0_RTS_N); + HAL_GPIO_OUTPUT_SET(GPIO_HSS1_RTS_N); + HAL_GPIO_OUTPUT_ENABLE(GPIO_HSS1_RTS_N); + + // Input / IRQ lines + HAL_GPIO_OUTPUT_DISABLE(GPIO_INPUT1); + HAL_GPIO_OUTPUT_DISABLE(GPIO_INPUT2); + HAL_GPIO_OUTPUT_DISABLE(GPIO_INPUT3); + HAL_GPIO_OUTPUT_DISABLE(GPIO_INPUT4); + HAL_GPIO_OUTPUT_DISABLE(GPIO_INPUT5); + HAL_GPIO_OUTPUT_DISABLE(GPIO_INPUT6); + HAL_GPIO_OUTPUT_DISABLE(GPIO_INPUT7); + HAL_GPIO_OUTPUT_DISABLE(GPIO_INPUT8); + HAL_GPIO_OUTPUT_DISABLE(GPIO_INPUT9); + HAL_GPIO_OUTPUT_DISABLE(GPIO_INPUT10); + + set_control(CONTROL_HSS0_DTR_N, 1); + set_control(CONTROL_HSS1_DTR_N, 1); + set_control(CONTROL_EEPROM_WC_N, 1); + set_control(CONTROL_PCI_RESET_N, 0); // unused on micro router + output_control(); + + hal_delay_us(10000); + + set_control(CONTROL_PCI_RESET_N, 1); // unused on micro router + output_control(); + +#ifdef CYGPKG_IO_PCI + extern void hal_plf_pci_init(void); + hal_plf_pci_init(); +#endif +} + + +#ifdef CYGPKG_DEVS_ETH_INTEL_NPE +int cyghal_get_npe_esa(int port, cyg_uint8 *buf) +{ + cyg_uint8 *flash = (cyg_uint8 *)FLASH_BASE; + + if (port != 0 && port != 1) + return 0; + + if ((*(cyg_uint32 *)(flash + CONFIG_HW_BITS) & + (port == 0 ? CONFIG_HW_HAS_ETH0 : CONFIG_HW_HAS_ETH1)) == 0) + return 0; // port not installed + + memcpy(buf, flash + (port == 0 ? CONFIG_ETH0_ADDRESS : + CONFIG_ETH1_ADDRESS), 6); + + // don't use broadcast address + if (buf[0] == 0xff && buf[1] == 0xff && buf[2] == 0xff && + buf[3] == 0xff && buf[4] == 0xff && buf[5] == 0xff) + return 0; + + return 1; +} + +#endif // CYGPKG_DEVS_ETH_INTEL_NPE --- a/redboot/current/src/version.c 2002-05-24 01:08:32.000000000 +0200 +++ b/redboot/current/src/version.c 2007-12-18 00:47:03.000000000 +0100 @@ -68,30 +68,15 @@ // outlined above. // -// Do not change the following two lines at all. They are fiddled by release -// scripts. -#define _CERTIFICATE Non-certified -//#define CYGDAT_REDBOOT_CUSTOM_VERSION current - -#if defined(CYGDAT_REDBOOT_CUSTOM_VERSION) -#define _REDBOOT_VERSION CYGDAT_REDBOOT_CUSTOM_VERSION -#elif defined(CYGPKG_REDBOOT_current) -#define _REDBOOT_VERSION UNKNOWN -#else -#define _REDBOOT_VERSION CYGPKG_REDBOOT -#endif - #define __s(x) #x #define _s(x) __s(x) char RedBoot_version[] CYGBLD_ATTRIB_WEAK = - "\nRedBoot(tm) bootstrap and debug environment [" _s(CYG_HAL_STARTUP) "]" - "\n" _s(_CERTIFICATE) " release, version " _s(_REDBOOT_VERSION) - " - built " __TIME__ ", " __DATE__ "\n\n"; + "\nRedBoot(tm) bootstrap and debug environment [" _s(CYG_HAL_STARTUP) "], built " __DATE__ "\n\n"; // Override default GDB stubs 'info' // Note: this can still be a "weak" symbol since it will occur in the .o // file explicitly mentioned in the link command. User programs will // still be allowed to override it. char GDB_stubs_version[] CYGBLD_ATTRIB_WEAK = - "eCos GDB stubs [via RedBoot] - built " __DATE__ " / " __TIME__; + "eCos GDB stubs [via RedBoot] - built " __DATE__;